The present invention relates to Universal Serial Bus (USB) devices, and, more particularly, to memory allocation in USB controllers.
A USB peripheral device is a peripheral device such as a mouse, keyboard, joystick, camera, scanner, printer, or data-storage device, that connects to a host computer via a USB connection (e.g., a USB cable) and in accordance with a USB Specification. The USB Specification provides technical details specifying the behavior and interactions of USB devices and hosts. The current revision is USB Specification 3.1, which is available online at http://www.usb.org/.
A host computer that is capable of interacting with a USB peripheral device includes at least one USB port and a host controller. A host's USB port can connect to a USB peripheral device or a USB hub.
Note that, as used herein, (i) “USB peripheral device” refers to a tangible and individually connectable USB device, while (ii) “USB device” refers to a USB device in any one of a variety of formats, including, for example, (a) a USB peripheral device, (b) a logical USB device that is not individually connectable but is individually addressable by the host controller, or (c) one of the varieties of USB devices described below.
A USB device typically includes at least one host-accessible function, such as, for example, human-interfacing, printing, scanning, or data storage. A USB hub connects to a host USB port upstream and multiple USB devices downstream, thereby expanding the number of USB devices that can connect to the host USB port.
A compound USB device is a type of USB device that internally incorporates a USB hub and one or more connected USB devices. As a result, to the host controller, the compound USB device appears as a hub with one or more permanently connected USB devices. A composite USB device, meanwhile, is a USB device that incorporates a plurality of host-accessible functions, but does not include a hub and has only one USB-device address. Note that a compound USB device may include, along with the incorporated hub, uniquely addressable single-function, composite, and/or compound devices.
Communication between a host and a USB device is performed through logical channels called pipes that are established between the host and logical endpoints in the USB device. A particular endpoint is identified by its USB device enumerator, endpoint enumerator, and endpoint direction. An endpoint's direction may be IN or OUT, where (i) an IN endpoint provides data in to the host, while (ii) an OUT endpoint receives data out from the host. An example of an endpoint identifier is “device 0 endpoint 0 IN.”
There are generally two kind of pipes: message and stream. Message pipes are used for control functions and use an IN/OUT pair of endpoints, typically endpoint 0 IN and endpoint 0 OUT. Stream pipes are used for data transfers to and/or from the USB device.
A USB device may support a plurality of pipelines. A conventional USB device may have up to 16 IN endpoints and 16 OUT endpoints for a total of 32 endpoints. The actual number of endpoints allocated depends on the particular hardware implementation. Different USB devices require a different number of endpoints.
All of the component USB devices in a conventional compound USB device are assigned at least the maximum number of endpoints that any component device requires. In other words, if a compound USB device comprises eight component USB devices and the maximum number of endpoints needed by any one of the eight component USB devices is eight, then, each of the eight component USB devices would be assigned eight endpoints. This allocation method is simple to implement and use.
FIG. 1 is a simplified schematic block diagram of an exemplary conventional compound USB microcontroller unit (MCU) 100 that is connected to a host computer (not shown). The USB MCU 100 comprises random-access memory (RAM) share subsystem 101 and eight USB devices 102, such as, for example, USB Device 102(0). The RAM share subsystem 101 comprises a Serial Interface (SI) engine 103, RAM module 104, and USB MCU core 105, which are modules involved in managing endpoints for the component USB devices 102. Each of the USB devices 102 is communicatively connected to the SI engine 103 of the RAM share subsystem 101. The SI engine 103 is connected to the RAM module 104, which, in turn, is connected to the USB MCU core 105.
The SI engine 103 is used in controlling the transfer of data between the USB devices 102 and a host. The USB MCU core 105 performs conventional processor control functions for the USB MCU core 105. In other words, the USB MCU core 105 is a processor core. The RAM module 104 provides random access memory for use by various modules of the USB MCU 100 in their assorted operations.
FIG. 2 is a schematic diagram of the RAM module 104 of FIG. 1. The RAM module 104 includes (a) USB RAM 201, which is a RAM segment dedicated for USB functions, such as endpoint management and USB data buffering, and (b) general purpose RAM 202. The USB RAM 201 has a capacity of 2,000 bytes. The USB RAM 201 comprises a buffer descriptor (BD) table 203 and an endpoint data buffer 204.
The BD table 203 comprises buffer descriptors organized in logical rows. Each buffer descriptor includes status and control information for its corresponding endpoint buffer. Buffer descriptors are identified by the identifier of the corresponding endpoint—in other words, by device enumerator, endpoint enumerator, and direction.
The maximum number of endpoints used by any one of the exemplary USB devices 102(0)-102(7) is eight. Consequently, each USB device 102 is allocated eight endpoints and the BD table 203 comprises 64 rows. If each buffer descriptor uses four bytes of data, then the BD table 203 is 256 bytes (=8*8*4), leaving 1,744 bytes for the endpoint data buffer 204 (=2,000 −256). If the maximum number of endpoints were 16 instead of 8, then the BD table would need to be 512 bytes (=16*8*4), which might require allocation of more than 2,000 bytes to the USB RAM 201, which would take up a larger portion of the RAM module 104, or would require replacing the RAM module 104 with a larger memory module.
Alternative methods of allocating endpoints and/or buffer descriptors may be useful.